Question:

How are GPIO irqs handled on the sa-1100 and sa-1110?

Answer:

there are 28 GPIO lines are accessable by Linux. each
GPIO has associated with a number, a bit mask, and an
irq. GPIO's are numbered 0 through 27.

from linux/include/asm-arm/arm-sa1100/SA-1100.h:

#define GPIO_GPIO0	GPIO_GPIO (0)	/* GPIO  [0]*/
#define GPIO_GPIO1	GPIO_GPIO (1)	/* GPIO  [1]*/
#define GPIO_GPIO2	GPIO_GPIO (2)	/* GPIO  [2]*/
#define GPIO_GPIO3	GPIO_GPIO (3)	/* GPIO  [3]*/
#define GPIO_GPIO4	GPIO_GPIO (4)	/* GPIO  [4]*/
#define GPIO_GPIO5	GPIO_GPIO (5)	/* GPIO  [5]*/
#define GPIO_GPIO6	GPIO_GPIO (6)	/* GPIO  [6]*/
#define GPIO_GPIO7	GPIO_GPIO (7)	/* GPIO  [7]*/
#define GPIO_GPIO8	GPIO_GPIO (8)	/* GPIO  [8]*/
#define GPIO_GPIO9	GPIO_GPIO (9)	/* GPIO  [9]*/
#define GPIO_GPIO10	GPIO_GPIO (10)	/* GPIO [10]*/
#define GPIO_GPIO11	GPIO_GPIO (11)	/* GPIO [11]*/
#define GPIO_GPIO12	GPIO_GPIO (12)	/* GPIO [12]*/
#define GPIO_GPIO13	GPIO_GPIO (13)	/* GPIO [13]*/
#define GPIO_GPIO14	GPIO_GPIO (14)	/* GPIO [14]*/
#define GPIO_GPIO15	GPIO_GPIO (15)	/* GPIO [15]*/
#define GPIO_GPIO16	GPIO_GPIO (16)	/* GPIO [16]*/
#define GPIO_GPIO17	GPIO_GPIO (17)	/* GPIO [17]*/
#define GPIO_GPIO18	GPIO_GPIO (18)	/* GPIO [18]*/
#define GPIO_GPIO19	GPIO_GPIO (19)	/* GPIO [19]*/
#define GPIO_GPIO20	GPIO_GPIO (20)	/* GPIO [20]*/
#define GPIO_GPIO21	GPIO_GPIO (21)	/* GPIO [21]*/
#define GPIO_GPIO22	GPIO_GPIO (22)	/* GPIO [22]*/
#define GPIO_GPIO23	GPIO_GPIO (23)	/* GPIO [23]*/
#define GPIO_GPIO24	GPIO_GPIO (24)	/* GPIO [24]*/
#define GPIO_GPIO25	GPIO_GPIO (25)	/* GPIO [25]*/
#define GPIO_GPIO26	GPIO_GPIO (26)	/* GPIO [26]*/
#define GPIO_GPIO27	GPIO_GPIO (27)	/* GPIO [27]*/

the GPIO's 0-10 have individual irq controls, however
the GPIO's 11-27 share a single irq control. to determine
which GPIO has sent an irq, a bit mask is assigned to
each GPIO number. the event mask is defined in the
SA-1100.h file.

from linux/include/asm-arm/arm-sa1100/SA-1100.h:

#define IC_GPIO0	IC_GPIO (0)	/* GPIO  [0]*/
#define IC_GPIO1	IC_GPIO (1)	/* GPIO  [1]*/
#define IC_GPIO2	IC_GPIO (2)	/* GPIO  [2]*/
#define IC_GPIO3	IC_GPIO (3)	/* GPIO  [3]*/
#define IC_GPIO4	IC_GPIO (4)	/* GPIO  [4]*/
#define IC_GPIO5	IC_GPIO (5)	/* GPIO  [5]*/
#define IC_GPIO6	IC_GPIO (6)	/* GPIO  [6]*/
#define IC_GPIO7	IC_GPIO (7)	/* GPIO  [7]*/
#define IC_GPIO8	IC_GPIO (8)	/* GPIO  [8]*/
#define IC_GPIO9	IC_GPIO (9)	/* GPIO  [9]*/
#define IC_GPIO10	IC_GPIO (10)	/* GPIO [10]*/
#define IC_GPIO11_27	0x00000800	/* GPIO [11:27] (ORed)*/


as you can see GPIO's 0-10 have individual masks applied, however
the GPIO's 11-27 have a single mask covering the range.

once the bitmask defined, the corresponding irq's are defined
in the irqs.h file.

from linux/include/asm-arm/arm-sa1100/irqs.h

#define	IRQ_GPIO0		0
#define	IRQ_GPIO1		1
#define	IRQ_GPIO2		2
#define	IRQ_GPIO3		3
#define	IRQ_GPIO4		4
#define	IRQ_GPIO5		5
#define	IRQ_GPIO6		6
#define	IRQ_GPIO7		7
#define	IRQ_GPIO8		8
#define	IRQ_GPIO9		9
#define	IRQ_GPIO10		10
#define	IRQ_GPIO11_27		11

again the GPIO's 0-10 have individual irq's assigned,and GPIO
irq for GPIO's 11-27 have been assigned a signal irq of 11.
even though GPIO's 11-27 use the same irq trigger, it is 
possible to identify which GPIO sent the trigger.


from linux/arch/arm/mach-sa1100/irq.c :

static void sa1100_GPIO11_27_demux(int irq, void *dev_id,
				   struct pt_regs *regs)
{
	int i, spurious;

	while ((irq = (GEDR & 0xfffff800))) {
		/*
		 * We don't want to clear GRER/GFER when the corresponding
		 * IRQ is masked because we could miss a level transition
		 * i.e. an IRQ which need servicing as soon as it is
		 * unmasked.  However, such situation should happen only
		 * during the loop below.  Thus all IRQs which aren't
		 * enabled at this point are considered spurious.  Those
		 * are cleared but only de-activated if they happen twice.
		 */
		spurious = irq & ~GPIO_11_27_enabled;
		if (spurious) {
			GEDR = spurious;
			GRER &= ~(spurious & GPIO_11_27_spurious);
			GFER &= ~(spurious & GPIO_11_27_spurious);
			GPIO_11_27_spurious |= spurious;
			irq ^= spurious;
			if (!irq) continue;
		}

		for (i = 11; i <= 27; ++i) {
			if (irq & (1<<i)) {
				do_IRQ(IRQ_GPIO11 + i - 11, regs);
			}
		}
	}
}


this section of code takes the shared irq11 and then checks to see
which GPIO triggered the irq, then creates an extended irq based on
the GPIO id plus 21.

Example: GPIO 27 is trigger
	 21+27=48
	 so IRQ_GPIO27=48

as demonstrated in the irqs.h file.

from linux/include/asm-arm/arm-sa1100/irqs.h

#define	IRQ_GPIO11		32
#define	IRQ_GPIO12		33
#define	IRQ_GPIO13		34
#define	IRQ_GPIO14		35
#define	IRQ_GPIO15		36
#define	IRQ_GPIO16		37
#define	IRQ_GPIO17		38
#define	IRQ_GPIO18		39
#define	IRQ_GPIO19		40
#define	IRQ_GPIO20		41
#define	IRQ_GPIO21		42
#define	IRQ_GPIO22		43
#define	IRQ_GPIO23		44
#define	IRQ_GPIO24		45
#define	IRQ_GPIO25		46
#define	IRQ_GPIO26		47
#define	IRQ_GPIO27		48

/*
 * To get the GPIO number from an IRQ number
 */
#define GPIO_11_27_IRQ(i)	((i) - 21)

once each GPIO 11-27 is assigned a unique extended irq, they
can be used throughout the code.


NOTE: system control i/o functions such as a power button should
      be placed on GPIO's 0-10 so that unrelated i/o irq's
      do not triger unintended results.


the following registers are used to setup and read the GPIO irq 
as they are needed in the system.

from linux/include/asm-arm/arm-sa1100/SA-1100.h:

/*
 * General-Purpose Input/Output (GPIO) control registers
 *
 * Registers
 *    GPLR      	General-Purpose Input/Output (GPIO) Pin Level
 *              	Register (read).
 *    GPDR      	General-Purpose Input/Output (GPIO) Pin Direction
 *              	Register (read/write).
 *    GPSR      	General-Purpose Input/Output (GPIO) Pin output Set
 *              	Register (write).
 *    GPCR      	General-Purpose Input/Output (GPIO) Pin output Clear
 *              	Register (write).
 *    GRER      	General-Purpose Input/Output (GPIO) Rising-Edge
 *              	detect Register (read/write).
 *    GFER      	General-Purpose Input/Output (GPIO) Falling-Edge
 *              	detect Register (read/write).
 *    GEDR      	General-Purpose Input/Output (GPIO) Edge Detect
 *              	status Register (read/write).
 *    GAFR      	General-Purpose Input/Output (GPIO) Alternate
 *              	Function Register (read/write).
 *
 * Clock
 *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
 */

#define GPLR		__REG(0x90040000)  /* GPIO Pin Level Reg.             */
#define GPDR		__REG(0x90040004)  /* GPIO Pin Direction Reg.         */
#define GPSR		__REG(0x90040008)  /* GPIO Pin output Set Reg.        */
#define GPCR		__REG(0x9004000C)  /* GPIO Pin output Clear Reg.      */
#define GRER		__REG(0x90040010)  /* GPIO Rising-Edge detect Reg.    */
#define GFER		__REG(0x90040014)  /* GPIO Falling-Edge detect Reg.   */
#define GEDR		__REG(0x90040018)  /* GPIO Edge Detect status Reg.    */
#define GAFR		__REG(0x9004001C)  /* GPIO Alternate Function Reg.    */


Sources:

Linux kernel source
SA-1100 and SA-1110 Developers Guide

special thanks to Russ Dill, Tim Riker, and Erik Mouw